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1 features ? fast interleave cycle time - 35 ns ? continuous memory interleaving C unlimited linear access data output ? dual voltage range operation C low-voltage power supply range, 3.0v to 3.6v or standard 5v 10% supply range ? low-power cmos operation C 108 mw max. active at 25 mhz for v cc = 3.6v C 14.4 mw max. standby for v cc = 3.6v ? jedec standard surface mount packages C 44-lead plcc C 40-lead vsop (10 x 14mm) ? high-reliability cmos technology C 2,000v esd protection C 200 ma latchup immunity ? rapid ? programming algorithm - 50 s/word (typical) ? cmos and ttl compatible inputs and outputs C jedec standard for lvttl ? integrated product identification code ? commercial and indvtustrial temperature ranges description the AT27LV1026 is a high performance 16-bit interleaved low-voltage 1,048,576-bit one-time programmable read only memory (otp eprom) organized as 2 x 32k x 16 bits. it requires only one supply in the range of 3.0v to 3.6v in normal read mode operation. rev. 0956fC01/99 1-megabit (2 x 32k x 16) 16-bit interleaved low-voltage otp eprom AT27LV1026 note: both gnd pins must be connected. pin configurations pin name function a0 - a15 addresses o0 - o15 outputs cs chip select rd read strobe ale address latch enable pgm program strobe nc no connect plcc top view 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 o12 o11 o10 o9 o8 gnd nc o7 o6 o5 o4 a13 a12 a11 a10 a9 gnd nc a8 a7 a6 a5 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 o3 o2 o1 o0 rd gnd a0 a1 a2 a3 a4 o13 o14 o15 cs vpp gnd vcc pgm ale a15 a14 vsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a9 a10 a11 a12 a13 a14 a15 ale pgm vcc vpp cs o15 o14 o13 o12 o11 o10 o9 o8 gnd a8 a7 a6 a5 a4 a3 a2 a1 a0 rd o0 o1 o2 o3 o4 o5 o6 o7 gnd
AT27LV1026 2 this device is internally architected as two 32k x 16 mem- ory banks, odd and even. to begin a non-linear access nla cycle, (which typically equals a minimum of two linear access la cycles), ale is asserted high and cs is asserted low. the two internal 15-bit counters store the address for the odd and even banks and increment alter- nately during each subsequent linear access la cycle. the la cycle will be terminated when cs is asserted high put- ting the device in standby mode, or another nla cycle starts. the la cycle can be resumed when cs is asserted low and ale stays low. the AT27LV1026 will continuously output data within each la cycle which is determined by the read rd signal. continuous interleave read operation is possible as there is no physical limit to the linear access la output. when the last address in the array is reached the counters will wrap around to the first address location and continue. for a nla cycle where a0 = 0 (ale asserted high, cs asserted low), both even and odd counters will be loaded with new address (a1 - a15). outputs (o0 - o15) from the even bank will be valid in t accnla within the nla cycle, the outputs from the odd bank will become valid in t accla within the following la cycle while the even counter increments by one to ready the data out for the next la cycle. the out- puts will have even or odd data alternating and the counters increment for the consecutive la cycles until cs is asserted high putting the device in standby mode, or a new nla cycle begins. for a nla cycle where a0 = 1 (ale asserted high, cs asserted low), the odd counter will be loaded with the new address (a1 - a15) while the even counter gets loaded with the new address+1. outputs (o0 - o15) from odd bank of memory will be valid in t accnla within the nla cycle, the data output from the even bank of memory will become valid in t accla within the following la cycle while the odd counter increments by one to ready the data out for the next la cycle. the outputs will have data from the odd or even memory bank alternately and the counters increment for the following consecutive la cycles until cs is asserted high putting the device in standby mode, or a new nla cycle begins. when coming out of standby mode, the device can either enter into a new nla cycle or resume where the previous la operation left off and was termi- nated by standby mode. system considerations switching under active conditions may produce transient voltage excursions. unless accommodated by the system design, these transients may exceed data sheet limits, resulting in device non-conformance. at a minimum, a 0.1 m f high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. this capacitor should be connected between the v cc and ground termi- nals of the device, as close to the device as possible. addi- tionally, to stabilize the supply voltage level on printed circuit boards with large eprom arrays, a 4.7 f bulk elec- trolytic capacitor should be utilized, again connected between the v cc and ground terminals. this capacitor should be positioned as close as possible to the point where the power supply is connected to the array. operating table if a0 = 0 at beginning of nla cycle: if a0 = 1 at beginning of nla cycle: and so on. and so on. consecutive cycle counter outputs consecutive cycle counter outputs even odd even odd nla address address from even bank nla address+1 address from odd bank la +1 - from odd bank la -+1 from even bank la - +1 from even bank la +1 - from odd bank la +1 - from odd bank la -+1 from even bank la - +1 from even bank la +1 - from odd bank standby hi-z standby hi-z la +1 - from odd band la - +1 from even bank la - +1 from even bank la +1 - from odd band
AT27LV1026 3 block diagram note: 1. minimum voltage is -0.6v dc which may undershoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc which may overshoot to +7.0v for pulses of less than 20 ns. 32kx16 memory array 32kx16 memory array mux logic 15 16 16 15 16 a0 cs data outputs o-o 015 ale a0 rd cs odd counter clk_even clk_odd even counter address input a-a 115 pgm vcc gnd vpp absolute maximum ratings* temperature under bias................................ -55 c to +125 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on a9 with respect to ground .......................................-2.0v to +14.0v (1) v pp supply voltage with respect to ground .......................................-2.0v to +14.0v (1)
AT27LV1026 4 notes: 1. x can be v il or v ih . 2. non-linear and linear access cycles, and standby modes require, 3.0v v cc 3.6v, or 4.5v v cc 5.5v. 3. refer to programming characteristics. programming modes require v cc = 6.5v. 4. v h = 12.0 0.5v. 5. two identifier words may be selected. all ai inputs are held low (v il ), except a9 which is set to v h and a0 which is toggled low (v il ) to select the manufacturers identification word and high (v ih ) to select the device code word. operating modes mode/pin ale cs rd pgm a 0 a 1 - a 15 v pp v cc outputs non-linear access cycle (2) v il v il v ih v il /v ih ai x v cc (2) d out linear access cycle (2) v il v il v ih x (1) xxv cc (2) d out standby (2) xv ih xv ih xxxv cc (2) high z rapid program (3) v ih v ih v il v il v il /v ih ai v pp v cc (3) d in pgm verify (3) v ih v il v il v ih v il /v ih ai v pp v cc (3) d out pgm inhibit (3) xv ih xv ih xxv pp v cc (3) high z product identification (3)(5) xv il xv ih v il /v ih a 9 = v h (4) a 1 - a 15 = v il v cc v cc (3) identification code dc and ac operating conditions for read operation AT27LV1026-35 AT27LV1026-45 AT27LV1026-55 operating temperature (case) com. 0 c - 70 c0 c - 70 c0 c - 70 c ind. -40 c - 85 c-40 c - 85 c-40 c - 85 c v cc power supply 3.0v to 3.6v 3.0v to 3.6v 3.0v to 3.6v 5v 10% 5v 10% 5v 10%
AT27LV1026 5 notes: 1. v cc must be applied simultaneously with or before v pp , and removed simultaneously with or after v pp . 2. v pp may be connected directly to v cc , except during programming. the supply current would then be the sum of i cc and i pp . dc and operating characteristics for read operation symbol parameter condition min max units v cc = 3.0v to 3.6v i li input load current v in = 0v to v cc 1 m a i lo output leakage current v out = 0v to v cc 5 m a i pp1 (2) v pp (1) read/standby current v pp = v cc 10 m a i sb v cc (1) standby current cs = v ih 5ma i cc v cc active current f = 25 mhz, i out = 0 ma, cs = v il 30 ma v il input low voltage -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 2.0 ma 0.4 v v oh output high voltage i oh = -2.0 ma 2.4 v v cc = 4.5v to 5.5v i li input load current v in = 0v to v cc 1 m a i lo output leakage current v out = 0v to v cc 5 m a i pp1 (2) v pp (1) read/standby current v pp = v cc 10 m a i sb v cc (1) standby current cs = v ih 8ma i cc v cc active current f = 25 mhz, i out = 0 ma, cs = v il 50 ma v il input low voltage -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 m a2.4v
AT27LV1026 6 notes: 1. 2, 3. - see ac waveforms for read operation. ac waveforms for read operation (1) notes: 1. refer to test waveforms and measurement levels diagram on next page. 2. this parameter is only sampled and is not 100% tested. 3. output float is defined as the point when data is no longer driven. 4. when reading a 27lv1026, a 0.1 m f capacitor is required across v cc and ground to suppress spurious voltage transients. ac characteristics for read operation v cc = 3.0v to 3.6v and 4.5v to 5.5v symbol parameter condition AT27LV1026 units min typ max t nlacyc non-linear access cycle 70 80 ns t lacyc linear access cycle ale = cs = v il 35 40 ns t ale ale high width 7.5 ns t as address/cs setup time 2.5 ns t ah address hold time 20 ns t ard ale low to rd low 4.5 ns t rdl rd low width ale = cs = v il 12 ns t rdh rd high width ale = cs = v il 12 ns t accnla address to output delay in non-linear address cycle from ale low 52 ns t accla output valid delay in linear address cycle from rd high ale = cs = v il 20 ns t df (2)(3) cs high to output float 14 ns t oh output hold from cs high 0 ns t cs output valid delay from cs low in linear address cycle 17 ns t rc rd high to cs falling edge delay 2 ns t cr cs falling edge to rd low delay 12 ns t ca cs rising edge to ale low delay 2.5 ns ale cs rd a 0-15 t ah t ale t as t ca t ard t rdl t oh t df t rc t cr t cs t rdh t accnla t nlacyc t lacyc t accla o 0 -15 valid nla la la la la
AT27LV1026 7 input test waveforms and measurement levels t r , t f < 2.5 ns (10% to 90%) output test load note: c l = 100 pf including jig capacitance. note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. 3.0v 0.0v 1.5v pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 410pfv in = 0v c out 812pfv out = 0v
AT27LV1026 8 programming waveforms (1) notes: 1. the input timing reference is 0.8v for v il and 2.0v for v ih . 2. t cs and t dfp are characteristics of the device but must accompanied by the programmer. 3. when programming the AT27LV1026 a 0.1 m f capacitor is required across v pp and ground to suppress spurious voltage transients. dc programming characteristics ta = 2 5 5 c, v cc = 6.5 0.25v, v pp = 13.0 0.25v symbol parameter test conditions limits units min max i li input load current v in = v il , v ih 10 m a v il input low level -0.6 0.8 v v ih input high level 2.0 v cc + 0.1 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 m a2.4 v i cc2 v cc supply current (program and verify) 50 ma i pp2 v pp supply current pgm = v il 30 ma v id a9 product identification voltage 11.5 12.5 v valid program (verify) read 6.5v 5.0v vih vil tds tas tdh tvcs tah 5.0v tvps tprt tpw 13.0v vil vih vih vil vih vil vil vih vih vil data out tdfp tcs data in tcss address stable address data v cc v pp rd pgm ale cs
AT27LV1026 9 notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. this parameter is only sampled and is not 100% tested. output float is defined as the point where data is no longer driven see timing diagram. 3. program pulse width tolerance is 50 m sec 5%. ac programming characteristics ta = 25 5c, v cc = 6.5 0.25v, v pp = 13.0 0.25v symbol parameter test conditions (1) limits units min max t as address setup time input rise and fall times (10% to 90%) 20 ns input pulse levels 0.45v to 2.4v input timing reference level 0.8v to 2.0v output timing reference level 0.8v to 2.0v 2 m s t css cs setup time 2 m s t ds data setup time 2 m s t ah address hold time 0 m s t dh data hold time 2 m s t dfp cs high to output float delay (2) 0 130 ns t vps v pp setup time 2 m s t vcs v cc setup time 2 m s t pw pgm program pulse width (3) 45 55 m s t cs data valid from cs 150 ns t prt v pp pulse rise time during programming 50 ns atmels 27lv1026 integrated product identification code codes pins hex data a0 o15-o8 o7o6o5o4o3o2o1o0 manufacturer 0 0 0 0 0 1 1 1 1 0 001e device type 1 0 0 1 1 0 0 0 0 1 0061
AT27LV1026 10 rapid programming algorithm a 50 m s pgm pulse width is used to program. the address is set to the first location. v cc is raised to 6.5v and v pp is raised to 13.0v. each address is first programmed with one 50 m s pgm pulse without verification. then a verification / reprogramming loop is executed for each address. in the event a word fails to pass verification, up to 10 successive 50 m s pulses are applied with a verification after each pulse. if the word fails to verify after 10 pulses have been applied, the part is considered failed. after the word verifies properly, the next address is selected until all have been checked. v pp is then lowered to 5.0v and v cc to 5.0v. all words are read again and compared with the original data to determine if the device passes or fails.
AT27LV1026 11 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 35 30 0.1 AT27LV1026-35jc AT27LV1026-35vc 44j 40v commercial (0 c to 70 c) 30 0.1 AT27LV1026-35ji AT27LV1026-35vi 44j 40v industrial (-40 c to 85 c) 45 30 0.1 AT27LV1026-45jc AT27LV1026-45vc 44j 40v commercial (0 c to 70 c) 30 0.1 AT27LV1026-45ji AT27LV1026-45vi 44j 40v industrial (-40 c to 85 c) 55 30 0.1 AT27LV1026-55jc AT27LV1026-55vc 44j 40v commercial (0 c to 70 c) 30 0.1 AT27LV1026-55ji AT27LV1026-55vi 44j 40v industrial (-40 c to 85 c) package type 44j 44-lead, plastic j-leaded chip carrier (plcc) 40v 40-lead, plastic thin small outline package (vsop) 10 x 14 mm
AT27LV1026 12 packaging information .045(1.14) x 45 pin no. 1 identify .045(1.14) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) ref sq .032(.813) .026(.660) .050(1.27) typ .022(.559) x 45 max (3x) .656(16.7) .650(16.5) .695(17.7) .685(17.4) sq sq *controlling dimension: millimeters 44j , 44-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 ac 40v , 40-lead, plastic thin small outline package (vsop) dimension in millimeters and (inches) jedec outline mo-142 ca
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